Pin layouts for an HSIO (High Speed Input/Output) require a large number of pins due in large part to isolation requirements. In high speed transmission/reception, differential signaling—which is a technique of transmitting information using complimentary pairs of signals—can be used. A single lane for operation at 6 to 8 Gbps (gigabits per second) speed typically includes one transmit pair of pins for differential signaling and one receive pair of pins also for differential signaling. Also, to meet signal integrity requirements, two to four ground pins are provided for isolation, for a total of six to eight pins per lane.
For higher speeds (25, 32, 50+ Gbps), more ground pins are added for isolation. Future generations of server chip can have many lanes (e.g., 96 to 192 lanes of PCIe (Peripheral Component Interconnect Express), proprietary chip to chip coherent interfaces, 10GE/40GE/100GE (Ten/Forty/One Hundred Gigabit Ethernet), COX (Cache Coherent Interconnect for Accelerators) or GenZ). At current speeds 576 to 1,152 pins may be driven. For yet higher speeds, even more pins will be necessary for additional lanes and to meet signal integrity requirements.